In a memory having a static RAM interface capable of reading data stored in an address after a certain access time in response to an input of the address, it is possible to employ a burst mode for increasing a speed of a reading operation. For example, an electrically writable flash memory has a burst buffer between a memory array and a data input/output terminal. In the reading operation, data selected from the memory array on a high order side of an address signal are transferred to the burst buffer and the data thus transferred to the burst buffer are selected on a low order side of the address signal and are output to an outside. It is possible to carry out the data output from the burst buffer by enabling an output enable signal. When the low order side of the address signal is changed within a range of a storage capacity of the burst buffer is changed in a state in which the output enable signal is maintained in “enable”, then, data held in the burst buffer are output to the outside. For example, when the burst buffer has a size of 16 bytes, data within an address range corresponding to 4 bits on the low order side in a byte address can be output from the burst buffer to the outside by a burst operation.
Patent Document 1 has described a flash memory capable of carrying out a burst read in a clock synchronization against an asynchronous read.
Patent Document 1: JP-A-11-339484 Publication